Efficient state reduction methods for PLA-based sequential circuits

Efficiency of State Assignment Methods for PLA-Based Sequential Circuits

Efficient state reduction methods for PLA-based sequential circuits - Computers and Digital Techniques [see also IEE Proceedings-Computers and Digital Techniques], IEE

/ Abstract: Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implemention of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the...

Efficient state reduction methods for PLA-based sequential circuits - Computers and Digital Techniques [see also IEE Proceedings-Computers and Digital Techniques], IEE

/ Abstract: Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implemention of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the...

Efficient Genetic Based Methods for Optimizing the Reversible and Quantum Logic Circuits

Various synthesis methods have been proposed in the literature for reversible and quantum logic circuits. However, there are few algorithms to optimize an existing circuit with multiple constraints simultaneously. In this paper, some heuristics in genetic algorithms (GA) to optimize a given circuit in terms of quantum cost, number of gates, location of garbage outputs, and delay, are proposed. ...

Efficient Genetic Based Methods for Optimizing the Reversible and Quantum Logic Circuits

Various synthesis methods have been proposed in the literature for reversible and quantum logic circuits. However, there are few algorithms to optimize an existing circuit with multiple constraints simultaneously. In this paper, some heuristics in genetic algorithms (GA) to optimize a given circuit in terms of quantum cost, number of gates, location of garbage outputs, and delay, are proposed. ...